Loading...
Courses

RTL Design Course

6.999.000₫
Dec03
RTL Design Course

Course Code: VS-RTL

Duration: 20 lessons

Tuesday, Thursday: 07:00 PM - 08:45 PM

Instructor: M.Eng. Ta Xuan Tung, Eng. Nguyen Nam Phuong

Target Audience

Fourth and fifth-year students in Electrical Engineering, Electronics, Information Technology, etc., who have a solid understanding of Digital Electronics, Computer Architecture, and VLSI.

Individuals aiming to pursue Digital IC Design (Soft IP) and who have completed the Digital Electronics course VS-DL or studied equivalent subjects at University.

Course Objectives

Equip students with knowledge of the Soft IP design process.

Use SystemVerilog language to design RTL (Register Transfer Level).

Design simple Soft IPs.

Analyze design outcomes.

Detailed Course Contents

Soft IP Design Process

How to write a Specification

SystemVerilog hardware description language:

⬥ Modeling

⬥ Signal classification

⬥ Arrays

⬥ Procedural blocks

⬥ Operators

⬥ Case

FSM (Finite State Machine) Design

Basics of Static Timing Analysis (STA)

Join Now
Testimonial

Our Students Say!