Course Code: VS-DV
Duration: 16 lessons
Coming soon
Instructor: Pham Ngoc Lam
Fourth and fifth-year students in Electrical Engineering, Electronics, Information Technology, etc., who have a solid understanding of Digital Electronics, Computer Architecture, VLSI and Hardware Description Languages such as Verilog/SystemVerilog
Individuals aiming to pursue Digital IC Design (Soft IP), who have completed the RTL Design course (VS-RTL) or equivalent university courses
Equip students with fundamental knowledge of verification, testbench writing, and verification planning
Use the hardware description language SystemVerilog to build verification environments
Flow, Testbench, Verification Plan
SystemVerilog for Verification:
⬥ Data Type
⬥ Control Flow
⬥ Process, Communication
⬥ Interface
OOPs
Randomization, Constraints
Coverage
Assertion
Misc Construct
HUST Student
The instructors are enthusiastic and highly knowledgeable. The practical exercises are very realistic and suitable for students. After the course, I was able to synthesize Verilog and run routing verification using the STDCELL library
HUST Student
The course is easy to follow for beginners, with many practical exercises. I gained a lot of valuable knowledge that I can apply to my real job, like fixing timing, power, and function issues
HUST Student
I find the Standard Cell Design course extremely helpful as the content supports my work significantly. I learned how to optimize and properly share MOS in layout, considering trade-offs
Teacher
The course has been very beneficial for my current job. I have been able to apply knowledge such as circuit analysis, optimization, circuit synthesis, timing checks, calculating setup and hold times for a circuit, and setting false paths
HUST Student
I am very satisfied with the course! The lectures are detailed, easy to understand, and the instructors communicate effectively. I learned how to write Verilog models for design, and I now can write RTL and functional tests for simple designs