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Basic SystemVerilog Verification

5.590.000₫
Comingsoon
Basic SystemVerilog Verification

Course Code: VS-DV

Duration: 16 lessons

Coming soon

Instructor: Pham Ngoc Lam

Target Audience

Fourth and fifth-year students in Electrical Engineering, Electronics, Information Technology, etc., who have a solid understanding of Digital Electronics, Computer Architecture, VLSI and Hardware Description Languages such as Verilog/SystemVerilog

Individuals aiming to pursue Digital IC Design (Soft IP), who have completed the RTL Design course (VS-RTL) or equivalent university courses

Course Objectives

Equip students with fundamental knowledge of verification, testbench writing, and verification planning

Use the hardware description language SystemVerilog to build verification environments

Detailed Course Contents

Flow, Testbench, Verification Plan

SystemVerilog for Verification:

⬥ Data Type

⬥ Control Flow

⬥ Process, Communication

⬥ Interface

OOPs

Randomization, Constraints

Coverage

Assertion

Misc Construct

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