Course Code: VS-SCA
Duration: 20 lessons
Coming soon
Instructor: Eng. Tran Van Tai, Eng. Phan Minh Nghia
Fourth and fifth-year students in Electrical Engineering, Electronics, Information Technology, etc., who have a solid understanding of Digital Electronics, Computer Architecture, and VLSI
Individuals aiming to pursue Digital IC Design (Hard IP)
Those who have completed Standard Cell Design Course (VS-SC) or equivalent University courses
Design schematic circuits
Design layout standard cells and understand the physical design flow
Characterization & release
Analyze, verify, and evaluate design results
Advanced CMOS knowledge.
Schematic design flow
⬥ Timing delay
⬥ Power
⬥ Setup and hold time
⬥ Fanout and load dependency
⬥ Noise
⬥ Design of complex circuits (flip-flops, multiplexers, decoders, etc.)
Standard cell layout design flow
⬥ Cell-level layout + Top-level layout
⬥ Optimization
⬥ Verification (DRC, LVS, QA)
⬥ Timing simulation
Characterization & release
⬥ RC extraction
⬥ Simulation: Analyze and measure the performance parameters of the cell
⬥ Create .lib and release the library
Physical design
⬥ Design planning
⬥ Place and route
HUST Student
The instructors are enthusiastic and highly knowledgeable. The practical exercises are very realistic and suitable for students. After the course, I was able to synthesize Verilog and run routing verification using the STDCELL library
HUST Student
The course is easy to follow for beginners, with many practical exercises. I gained a lot of valuable knowledge that I can apply to my real job, like fixing timing, power, and function issues
HUST Student
I find the Standard Cell Design course extremely helpful as the content supports my work significantly. I learned how to optimize and properly share MOS in layout, considering trade-offs
Teacher
The course has been very beneficial for my current job. I have been able to apply knowledge such as circuit analysis, optimization, circuit synthesis, timing checks, calculating setup and hold times for a circuit, and setting false paths
HUST Student
I am very satisfied with the course! The lectures are detailed, easy to understand, and the instructors communicate effectively. I learned how to write Verilog models for design, and I now can write RTL and functional tests for simple designs